A Programmable Logic Device (PLD) comprises a number of relatively simple logic modules with an arrangement to interconnect them in any of a wide variety of ways through a general purpose interconnection network to perform logic functions which can be quite complex. In addition, some of the logic modules include additional logic elements for concatenating the outputs of multiple modules to perform relatively complex logic functions without having to make use of the general purpose interconnection network. This additional logic is termed “Cascade Logic” and is used to implement high-speed, simple logic functions involving a large number of inputs.
U.S. Pat. No. 5,258,668 discloses a method for cascading logic units in which each logic module includes additional logic elements for forming a logical combination of the normal output signal of that logic module and the output signal from another, adjacent logic module. The output signal from the other logic module is applied directly to the additional logical element in the first logic module. The output signal of the additional logic elements in each logic module becomes the output signal of the logic module. As shown in FIG. 1, Block 20 is a 4-input look up table (LUT) providing an output 32, connected to the input of cascade logic element 22. The second input to the cascade logic element 22 is the cascade output 44 of another, preferably adjacent, programmable logic block (PLB). The cascade logic element 22 can be any desired logic gate, such as an AND gate. The logic element 22 logically combines the two signals 32 and 44 and applies the result either to a D flip flop or to the Cascade input 44 of the next PLB. The cascade output 44 or the flip flop output 38 is inverted and can be used as feedback for the LUT 20, and also serves as the logic module output 42. This method does not provide the flexibility to use the LUT output 32 and the cascade function output 44 simultaneously. That is, the LUT output is not available for other logic functions if the cascade function is implemented. In such situations, additional LUT logic is necessary to produce the required output, resulting in increased cost and delay.
FIG. 2 describes another prior-art implementation in which the cascade input 72 is gated by elements 74a and 74c. Element 74b is a programmable bit, which is programmed to indicate whether or not connection of the cascade in input to the cascade module 60 is desired. If connection of the cascade input 72 to the module 60 is desired, bit 74b is programmed to enable transistor 74a and disable transistor 74c. This applies the cascade input signal 72 to logic element 60, which here is an AND gate. The other input of block 60 is the output of LUT 50. The AND gate applies the ANDed output of the two inputs to node 76, which is the cascaded output. If connection of the cascade input 72 to the cascade logic 60 is not required, then the bit 74b is programmed to disable transistor 74a and enable transistor 74c. This applies Vcc to the second terminal of the AND gate, thereby allowing that gate to pass the output of the LVT 50 to the flip flop 70. But as with the arrangement of FIG. 1, in this arrangement only one of the outputs, that is, either the cascaded output or the LUT 50 output is available at any one time.